Job Title: Senior Digital Design Engineer
Location: Cambridge, UK
Job Type: Permanent, Minimum 3 days on site with flexible hybrid working
Salary: 60-80K Sterling
Job Description:
As a Senior Digital Design Engineer, you will implement high-performance AI inference solutions on FPGA. You will contribute to the IP library in SystemVerilog and build complete FPGA design solutions for customers. You will work as part of a diverse team of developers and researchers on IP that is core to inference products.
You will deliver highly performant, well-tested, and extensible code for widely deployed AI in modern data centres. You’ll collaborate with software and machine learning engineers, integrating against the client's compiler/runtime/driver stack to build high-reliability, low-latency, and high-throughput inference applications.
You will work with the latest AI-capable FPGAs from multiple vendors to develop RTL in SystemVerilog. You will generate maintainable and parameterizable IP components to enable reuse across multiple FPGAs and applications.
You will package IP into full solution implementations, achieve timing closure through floor planning, and test solutions on the board. You will make low-level software interface code changes to support integration with the client's software stacks. You will work in a Linux development environment.
You will help define the ways of working in the FPGA team, including coding standards and tests. You will help the team plan activities using Agile scrum methodology.
Responsibilities:
- Writing and testing IP components in SystemVerilog for FPGA
- Building full applications for FPGA using our IP library
- Integrating with third-party IP for external memory PCIe subsystems
- Extending IP verification code and integrating into automated test environments
- Working with software interface routines to support FPGA integration into the software stacks
- Learning about a range of Machine Learning inference optimization techniques
- Providing technical support for customer engagements
Recommended Experience and Skills:
- At least 5 years of experience generating clear, well-documented, and well-tested SystemVerilog, Verilog, or VHDL code
- Master's degree in Engineering, Mathematics, or other Scientific Discipline
- Experience with FPGA EDA tools such as Quartus or Vivado
- Experience with software languages such as C, C++, Python
- Familiarity with Linux development environments, version control, and CI systems
- Experience of bringing up full FPGA designs and debugging on hardware
- Experience optimizing RTL designs to achieve timing closure
- Good verbal and written communication skills
- (Nice to have) Familiarity with neural network architectures
- (Nice to have) Interest in Functional Programming Languages
If this job suits you and you are interested, please apply.
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