Exp: 3+ years
Location: Bangalore
Short notice preferred
JD: Candidate with 3+ yrs exp in Synthesis/STA role
Experience in handling complex data path-oriented multi-million gate synthesis
Working Knowledge of Physical synthesis using tools like Genus, Fusion Compiler
Experience in debugging for multi-clock domains hierarchical/flat timing analysis.
Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts.
Good Experience in synthesis timing closure and interactions with DFT and PD.
Good knowledge of analyzing trade-offs and recipes for timing/area/power/congestion.
Exposure to TCL scripting for usage in Synthesis/STA
Good team player. Need to interact with the stakeholders proactively.
Good verbal and written communication skills
Ability to debug and solve issues independently.