Hi All,
We are looking for PD(Front-end Synthesis ) Engineers/Leads.
Fullchip rollup , Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design
Fullchip timing - PrimeTime constraints, clocks.
Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains.
Voltage Island - Coarse level UPF/ Clock gating.
Exp: 8+ Yrs.
Location: Wipro India.