- Responsible for understanding micro architectural details of designs, developing re-usable test bench components
- Creates efficient test plans for RTL validation and Gate level simulations
• Executing test plans and reporting bugs to drive the development of flawless designs
• Responsible for executing RTL verification and GLS activities, which includes but not limited to
• Creation/modification of the testbench.
• Implementation of software/programming sequence.
• Creation/integration of checkers and scoreboards from unit level UVM environment.
• Resolution of compile and simulation errors.
• Innovative optimizations to reduce simulation time.
• Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to
Testbench/programming sequence in close collaboration with unit verification engineers, logic designers and architects.
• Will be actively involved in identifying and addressing verification pain points and creatively improving the end-to-end verification methodologies
• Close collaboration with the emulation team to enable emulation and timely debug of full chip test cases.
Required Skills :
• Test bench architecture and bus functional models development
• Proficient in coding Pre-Silicon functional validation tests to verify design to meet spec. requirements Creates efficient test plans for RTL validation and Gate level simulations
• Expertise in verification of design blocks (IP) and Subsystems for SoC(s)
• Expertise in SoC level validation
• Expertise in System verilog , UVM, and/or OVM based verification methodologies
• Experience in OOPs concepts, coverage driven constrained random validation
• Good knowledge on AMBA standards (AXI, AHB, APB)
• Working experience in any of these domains desirable CPU (Cortex A*, GIC600, ARM NIC), PCIe, USB, CSI, LPDDR4/HBM3
• Working knowledge of scripting, SVA
• Looking for highly motivated individuals and ability to deal with ambiguity
• Ability to work with external stakeholders for different verification components/test development
EXP - 7Yrs-10Yrs
Location - Bangalore