Title: DFT Engineer / Sr.Engineer / Lead / Principal Engineer
Exp 4 to 10 yrs.
- Should have worked hands-on ASIC DFT design,
implementation, vector generation/verification, JTAG, boundary scan and simulation.
-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.
- Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets.
- Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
-Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
-Excellent problem solving and debugging skills. Proactive in nature
- Excellent Customer interaction, Communication and Team work skills